The present invention relates to drive units, and in particular those which are formed of integrated circuits used for a liquid crystal display (LCD), being cascaded to latch a large amount of data serially sent and outputting the data in parallel, and which are featured by improved operation speed and reduced power consumption.
For drive units of which a large number of outputs is required, such as those used for driving a liquid crystal display, drive units having data latch circuits converting data serially supplied from a data generator into parallel data are used.
The drive units having data latch circuits are formed of large-sized integrated circuits having about 100 pins. With integrated circuits having 100 pins, the number of the outputs is not more than about 80. Where the number of the pins is 180 by means of TAB (tape automated bonding), the number of the outputs is not more than about 160.
To form a system handling data of a large number of bits, such as 64 bits, 4 to 8 integrated circuits, each having 80 to 160 outputs need to be cascaded.
An example of this type of circuit is proposed by the present inventor in Japanese Patent Application No. H01- 326580 and in U.S. patent application Ser. No. 07/627,408, filed Dec. 14th, 1990 now U.S. Pat. NO. 5,164,970. This will be described with reference to the drawings.
FIG. 1 is a block diagram showing a drive system comprising a plurality of drive units DC-1 to DC-N cascaded with each other. Each of the drive units DC-1 to DC-N are in the form of IC's (integrated circuits). The number N of the drive circuits could be 16, for example.
FIG. 2 is a circuit diagram showing the first prior art drive units cascaded with each other. FIG. 3 is a waveform diagram showing the operation of the various parts in FIG. 2. The following describes the first-stage drive unit DC-1 and the second-stage drive unit DC-2. But, the description of these drive units is generally applicable to any one of the drive units DC-1 and the drive unit DC-(i+1) in the next stage. The circuit of the next stage drive unit DC-2 has a configuration which is identical to the initial stage drive units DC-1, so its illustration is omitted.
In FIG. 1 and FIG. 2, data DS serially transmitted form a data generator, not shown, are applied to input terminals T1 of all the drive units DC-1 to DC-N. The clock pulses CP and latch pulses LP which are generated from the data generator are applied to the input terminals T2 and T3 of all the drive units DC-1 to DC-N. The clock pulses CP and the latch pulses LP are supplied in synchronism with the serial data DS. The latch pulses are for latching the serial data DS.
An enable signal is output from a terminal T5 of each drive unit DC-1 and is supplied to a terminal T4 of the drive unit DC-(i+1) of the next stage. In the case of the initial-stage drive unit DC-1, there is no preceding stage, and the enable input terminal T4 is grounded (connected to a logic Low level).
The serial data DS supplied to the input terminal T1 is supplied to a data latch circuit 1 via a buffer A1. The data latch circuit 1 is comprised of a plurality of flip-flops (FF's) 26 to 30 serving as latching means. For the FF's 26 to 30, data FF's or data latches are used, and serial data DS is input to the data input terminals D of the respective FF's.
The latch pulses LP applied to the input terminal T3 are supplied via buffer A3, to an operation/non-operation discrimination circuit 2, an enable latch circuit 4, a shift register or counter circuit 5, an enable signal output circuit 6, a latching driver 7 and a frequency divider circuit 8.
The shift register 5 is comprised of FF's 15 and 17 to 21, and an AND gate 16. The latch pulse LP is applied to the set input terminal S of the FF 15, and to the reset input terminals R of the FF's 17 to 21. The FF's 15 and 17 to 21 are connected so that the signal from the output terminal Q of each FF is input to the data input terminal D of the next FF. The data input terminal D of the first FF 15 is grounded (connected to the Low level).
Of the signals output from the output terminals Q of the FF's 15, 17 to 20, the Q outputs of the FF's 17 to 20 are supplied to the latch input terminals L of the FF's 27 to 30 forming the data latch circuit 1. The Q output of the FF 15 is supplied via the AND gate 16 to the latch input terminal L of the FF 26 in the data latch circuit 1.
Supplied to one input terminal of the AND gate 16 is the output of a three-input AND gate 14 forming the clock control circuit 3, and at the timing when the output of the AND gate 14 is at a logic High level, the Q output signal of the FF 15 is supplied to the latch input terminal L of the FF 26.
The clock control circuit 3 is comprised of the three-input AND gate 14 and OR gate 13, and produces operation clock signals on the basis of the clock pulses CP, the output signal of the operation/non-operation discrimination circuit 2, the output signal of the enable latch circuit 4 and the inverted Q terminal output signal of the FF 21 at the last stage in the shift register 5.
The shift clock signal output from the clock control circuit 3 is supplied not only to the AND gate 16, but also to the clock input terminals of the FF's 15 and 17 to 21.
The operation/non-operation discrimination circuit 2 makes a judgment as to whether the serial data supplied from the data generator are to be supplied to the circuit of this stage or of the next-stage. The operation/non-operation discrimination circuit 2 is comprised of three D-type FF's 9 to 11.
The frequency divider circuit 8 frequency-divides the clock pulses, the decimates the clocks for receiving the enable signal, so that the effect of the delay time of the enable signal is avoided, and is comprised of a D-type FF 75 and a two-input AND gate 76.
The enable latch circuit 4 is provided to latch, in response to the output of the frequency divider circuit 8, the enable signal supplied to the input terminal T4, and is comprised of a D-type FF 12.
The output signal from the Q output terminal of the FF 19 at the third last stage is supplied to one input terminal of a NOR gate 23 forming the enable signal output circuit 6. The enable signal output circuit 6 is comprised of the NOR gate 23, a NOR gate 22 and an inverter 24. The NOR gates 23 and 22 form an R-S FF 61. The output of the inverter 24 is output of the terminal T5, and is supplied as the enable signal to the input terminal T4 of the succeeding stage.
The operation of the drive unit DC-1 will now be described.
The serial data DS, the clock pulse signal CP, and the latch pulse signal LP sent from the data generator are of the waveforms as shown in FIG. 3, the waveforms being continuous.
When the latch pulse LP is input, the FF's 10, 75, 12, and 17 to 21 are reset during the High level part of the latch pulse, so the Q output terminals of these FF's go Low.
In the case of the FF 21, the inverted Q output goes High, and this signal is sent to the first input terminal of the AND gate 14. The R-S FF 61 is also reset and its Q output goes Low, and is output via the inverter 24, so that a High signal is output at the terminal T5.
The FF 15 is set by the High level of the latch pulse and the Q output terminal goes High.
When the latch pulse LP later goes Low, the Q output of the FF 9 goes High, and is sent to the D input terminal of the FF 10. At the same time, the serial data DS having been latched at the latch circuits 26 to 30 are then latched by the latching LCD driver 7, and signals of the LCD drive levels are output from the output terminals 32 to 36.
At the rising edges of the clock pulses CP sent from the data generator, the serial data DS sent from the data generator are input to the D input terminals of the respective FF's of the data latch circuit 1.
The enable input terminal T4 of the initial-stage drive unit DC-1 is set at the Low level, and this Low level is inverted at the inverter A4 to become a High level, which is sent to the D input terminal of the FF's 11 and 12. Once the Q output terminal of the FF 10 goes Low, the Q output of the FF 11 goes High and remains High. The High level output is sent to the first input terminal of the two-input OR gate 13 whose output is connected to the second input terminal of the three-input AND gate 14.
The first input terminal of the three-input AND gate 14 is High, so the clock pulses CP applied to the third input terminal of the AND gate 14 is gated through without change.
Applied to the input terminal T4 of the next-stage drive unit DC-2 is a High enable signal from the output terminal T5 of the initial-stage LCD drive unit DC-1. The High signal is inverted at the inverter A4 into a Low signal, which is then applied to the D input terminals of the FF's 11 and 12. Once the Q output of the FF 10, which is applied to the clock input terminal of the FF 11, falls from High to Low, the Q output of the FF 11 goes Low and remains at the Low level, as mentioned above, and is supplied to the first input terminal of the two-input OR gate 13.
The Q output of the FF 12 applied to the second input terminal of the OR gate 13 is Low, so the output of the two-input OR gate 13 is Low.
At the three-input AND gate 14 to which the output of the two-input OR gate 13 is supplied, the AND condition is not satisfied, so the clock pulses CP being applied to the third input terminal of the AND gate 14 are not gated through.
If a clock pulse CP is input to the initial-stage drive unit DC-1, it is sent via the AND gate 14 to the second input terminal of the two-input AND gate 16. Since the first input terminal of the two-input AND gate 16 is receiving a High signal, the output of the two-input AND gate 16 will be High. When the clock pulse falls from High to Low, as shown in FIG. 3, the Q output of the FF 15 goes Low. The output of the two-input AND gate 16 will then be Low, and is sent to the latch input terminal L of the FF 26, so the first bit of serial data DS is latched. At the same time the Q output of the FF 17 goes High. Concurrently therewith, the Q output of the FF 10 goes High to reset the FF 9. Similarly, the FF 75 increments its count by one, and its Q output goes High.
The FF's 9, 10 and 75 in the other drive units DC-2 to DC-N function in the same manner.
When the second bit of the serial data DS and clock pulse CP are sent, the Q output of the FF 17 goes Low and the Q output of the FF 18 goes High. The Q output of the FF 17 is applied to the latch input terminal of the FF 27, so the second bit of the serial data DS is latched by the FF 27. In put then to the first input terminal of the two-input AND gate 76 to which the Q output of the FF 75 is input is a High signal, so the clock pulse to the second input terminal is passed through the AND gate 76 and input to the clock input terminal of the FF 12. The FF 12 reads the High level (inverted T4 signal) at th data input terminal and outputs it via its Q output. Subsequently, at every even clock pulse, the signal at the T4 terminal is read, by means of the FF's 75 and 12 and the AND gate 76, and a High signal is output to the second input terminal of the OR gate 13.
Concurrently therewith, the FF 10 reads the Low signals at the Q output of the FF 9, and outputs it via its Q output. At the falling edge thereof, the FF 11 reads the inverted logic level (High level in this case) of the signal input to the T4 terminal and supplies it to the first input terminal of the OR gate 13.
In the next-stage drive unit DC-2, similar functions are performed by means of the FF's 9, 10, 11, 75 and 12 and the AND gate 76, and the Low signal is latched by the FF's 11 and 12, and output to the OR gate 13.
The input signals to the OR gate 13 are both Low, so the second input terminal of the three-input AND gate is Low, prohibiting passage of (i.e., blocking) the clock pulse CP signal at the third input terminal.
When the third bit of the serial data DS and clock pulse CP are sent to the initial-stage drive units DC-1, the Q output of the FF 18 goes Low and the Q output of the FF 18 is supplied to the latch input terminal of the FF 28, so the third bit of the serial data is latched by the FF 28. In this way, the serial data DS sent from the data generator are successively latched by the respective FF's 26 to 30 in the data latch circuit 1 in synchronism with the clock pulses CP. When the last-but-one bit of the serial data is input the initial-stage drive unit DC-1 (when the laser-but-two clock is input) the Q output of the FF 19 goes High and is transmitted to the two-input NOR gate 23 of the R-S FF 61, which is thereby set, and a Low signal having been obtained by inversion at the inverter 24 is output via the terminal T5, and is transferred to the terminal T4 of the next stage. This signal is the enable signal for the next stage, and is passed via the input terminal T4 of the next-stage drive unit DC-2, and, in the same way as the initial-stage drive unit DC-1, is applied via the inverter A4 to the respective D input terminals of the FF's 11 and 12.
When a clock pulse CP is further input, the Q output of the FF 19 goes Low and is applied to the latch input terminal of the FF 29, so the last-but-one bit is latched by the FF 29. Concurrently therewith, the Q output of the FF 20 goes High. The Q output of the FF 75 in the next stage then goes High, but the AND gate 76 does not output a pulse.
When the clock pulse CP is input, the Q output of the FF 20 goes Low, and this Q output of the FF 20 is applied to the latch input terminal of the FF 30, so the last bit DS for the initial stage is latched in the FF 30. The Q output of the FF 21 goes High and the inverted Q output of the FF 21 goes Low. The inverted Q output signal of LOW level is applied to the first input of the three-input AND gate 14 as an end signal. As a result, the clock pulse CP sent from the data generator is blocked at the three-input AND gate 14.
Concurrently, since the Q output of the FF 75 of the next-stage drive unit DC-2 is High, the clock pulse CP is transmitted via the AND gate 76 to the clock input terminal of the FF 12, so at the falling edge of the clock pulse CP, the FF 12 latches the High signal obtained by inverting the enable signal, and transmits it via its Q output, and via the second input terminal of the two-input OR gate 13 to the second input terminal of the three-input AND gate 14. Since the first input terminal of the AND gate 14 is also High, the clock pulse sent from the data generator is passed through the thee-input AND gate 14, and is sent to the clock input terminals of the FF's 15, and 17 to 21 and the second input terminal of the two-input AND gate 16.
The clock pulse next sent from the data generator is the pulse on which the next stage begins to operate. At the falling edge of this clock pulse, the Q output of the FF 15 falls, and the Q output of the FF 17 goes High. A High signal has been applied to the first input of the two-input AND gate 16, up to the falling edge of the clock pulse, so the clock pulse is passed, only once, through the AND gate 16 and input to the latch input terminal of the FF 26. Input to the D input terminals of the FF's 26 to 30 are serial data DS from the data generator, so in the next-stage drive unit DC-2, the FF 26 latches the data DS at the falling edge of the clock pulse CP, and sends it via its Q output to the driver 7.
When the clock pulse CP is next sent from the data generator, the Q output of the FF 17 goes Low, the Q output of the FF 18 goes High, and a serial data DS corresponding to the clock pulse CP is latched by the FF 27. Subsequently, the serial data DS are successively latched at the clock pulses CP in a similar manner.
When the last-but-two clock pulse CP that is input to the second-stage drive unit DC-2 is input, the Q output of the FF 19 at the last-but-two stage in the shift register 5 goes High. From this High signal, the R-S FF 61 is set, and this High signal is passed through the inverter 24 to become a Low signal, which is sent via the output terminal T5 to the enable input terminal T4 of the third-stage drive unit DC-3 (not illustrated as such).
When the clock pulse CP is next sent from the data generator, the Q output of the FF 19 of the second-stage drive unit DC-2 goes Low and the Q output of the FF 20 goes High. Then, the Q output of the FF 19 is sent to the latch terminal L of the FF 29, and the serial data corresponding thereto is latched by the FF 29.
When the clock pulse CP is next sent from the data generator, the Q output of the FF 20 goes Low and the Q output of the FF 21 goes High, and its inverted Q output goes Low. Then, the Q output of the FF 20 is sent to the latch terminal L of the FF 30, and the serial data corresponding thereto is latched by the FF 30.
The inverted Q output (Low) of the FF 21 is applied to the first input terminal of the three-input AND gate 14, so the output of the three-input AND gate 14 is fixed at the Low level. As a result, the clock pulse CP sent from the data generator is blocked at the three-input AND gate 14.
The Q outputs of the FF's 26 to 30 are sent to the latching driver 7.
Subsequently, when the latch pulse LP is sent from the data generator after the data is sent to the drive units in the third and subsequent stages, the drive unit circuit 7 latches the data being input from the data latch circuit 1 and outputs them in parallel via the output terminals 32 to 36.
As has been described, in the prior art drive unit, for the purpose of reducing power consumption, enable signals are used to permit input of the clock only to the drive unit to latch the data sent from the data generator and output the data, and to prohibit the clock from being input to other drive units.
Accordingly, when the power supply for the logic circuit is 5 V, the power supply of the drive unit is 40 V, the LCD is not connected, and the clock pulse frequency is 3 MHz, the consumption current at the time of operation is about 5 mA, and is about 2 mA in the state in which the clocks are not accepted.
In the prior art example, one bit of serial data is transferred. But with the increase in size of the LCD screen, increases to four bits of serial data, eight bits of serial data, and so on is possible, and the frequency of the clock pulse CP of 3 MHz may be increased to 6 MHz, 8 MHz, and so on.
With an increase in the clock pulse CP frequency, the consumption current is increased from 5 mA (3 MHz), to 10 mA (6 MHz), and to 13 mA (8 MHz). Similarly, in the state in which the clocks are not accepted, it is increased from 2 mA (3 MHz) to 4 mA (6 MHz) and to 5 mA (8 MHz). With an increase in the number of bits, the consumption current is increased from 13 mA (1 bit) to 19 mA (4 bits), to 27 mA (8 bits) and to 35 mA (12 bits). In the state in which the clocks are not accepted, it is increased from 5 mA (1 bit) to 11 mA (4 bits), to 19 mA (8 bits), and to 27 mA (12 bits).
This is a problem yet to be solved for the reduction of the power consumption in the drive unit for a large-screen LCD display.
Another problem associated with the prior-art circuit is encountered when it is implemented on an integrated circuit using a 4 .mu.m MOS process.
When the frequency of the clock pulses CP is high, e.g., 6 MHz, the clock pulses CP input to the third input terminal of the AND gate 14 in the clock control circuit 3 are passed through the AND gate 14 and transmitted as shift clock pulses to the clock input terminals of the FF's 15 and 7 to 21. Assume that the last bit of shift data DS is to be read into the latch 30. The last pulse CP for this drive unit turns the Q output of the FF 20 from High to Low, while the FF 21 latches the Q output of the FF 20 and outputs, via its inverted Q output, a Low signal. This Low signal is transmitted to the first input terminal of the AND gate 14, and when the clock pulse next rises High, the output of the AND gate 14 remains at the Low level. However, in the 4 .mu.m C-MOS process, the sum of the delay from the third input terminal of the AND gate 14 to the output terminal, the delay of the shift clock pulse over the wiring conductor (the signal delay due to the load capacitance of the FF's 15 and 17 to 21, and the wiring conductors), the delay of the inverter Q output with respect to the clock input terminal of the FF 21, and the signal propagation delay time over the wiring conductors from the inverted Q output of the FF 21 to the first input terminal of the AND gate 14 is about 88 ns, so the third input terminal of the AND gate 14 goes High about 5 ns before the first input terminal of the AND gate 14 falls. The period of 6 MHz is 166 ns, but with the duty ratio of 50% the period of the Low level the clock pulse is only 83 ns, so the High level of the clock pulse CP is passed through the AND gate 14 to the clock input terminals of the FF's 15, 17 to 21. After 5 ns, the Low signal is input to the first input terminal of the AND gate 14, whereupon the output of the AND gate 14 goes Low. Because of these timing problems, the output of the AND gate 14 contains a spike-like pulse of a short period. The spike-like pulse is transmitted to the clock input terminals of the FF's 15 and 17 to 21, but as the data input terminals of the FF's 15 and 17 to 21 are all Low, the Q outputs of the FF's 15 and 17 to 21 are all Low and the inverted Q output of the FF 21 is High. As a result, the inverted Q output of the FF 21 is again transmitted to the first input terminal of the AND gate 14, so the prohibition of the input of the clock uplse CP to the third input terminal of the AND gate 14 is nullified, and the clock pulses are thereafter continuously passed through the AND gate 14 and transmitted as shift clocks to the clock input terminals of the FF's 15 and 17 to 21. The Q outputs of the FF's 15 and 17 to 21 are Low, so the data latches 26 to 30 of the data latch circuit 1 do not read the shift data DS. When the latch pulse LP is input, the outputs of the data latch circuit 1 are passed through the drive 7, and output via the output terminals 32 to 36. These outputs are not associated with abnormality, and no erroneous results are output to the outside, but internally the prohibition of the input to the clock pulses is failing and the power consumption savings are not achieved.
With such failure of power consumption saving, when the power supply for the logic circuit is 5 V, the power supply for the drive unit is 40 V, the LCD is not connected, and the clock pulse frequency is 3 MHz, the consumption current at the time of operation is about 5 mA, and is about 2 mA in the state in which the clocks are not accepted. It is expected that the consumption current is about 4 mA when the clock pulses are not accepted, if the clock pulse frequency is 6 MHz and the consumption current is about 10 mA when the clock pulses are gated through. But in fact, the consumption current int he state in which the clock pulses are not accepted is about 10 mA. This has been an obstacle to reduction in power consumption in a large-sized LCD display using about 16 drive units (IC's).